During design, a layout of an integrated circuits (IC) is typically drawn or rendered in two dimensions from a “top” view of the circuit. In such a view, only one surface of various surface features, such as, without limitation, transistors or interconnect lines, is shown. Thus, such a top view does not illustrate the thickness of circuit features. Additionally, ICs are typically formed of multiple layers, with different circuit features being on different layers. Depending on the topology and number of layers in an IC design, a top view of the design may not provide adequate visualization of the layers. This is particularly the case as IC design becomes more complex and involves more layers.
Three dimensional and sectional renderings of the various layers in an IC, and the thickness of those layers, can be important to allow understanding or complicated IC designs that may include complex interconnect and device structures. Also, a three dimensional rendering can enable faster checking and debugging of non-standard layouts.
Conventional computer aided design (CAD) tools allow an IC design to be laid out in two dimensions. Typically, conversion from such a two dimensions layout drawing into a three dimensional or sectional layout drawing cannot be carried out by such CAD tools. Some CAD type tools do have some capability to convert a two dimensional layout rendering into a three dimensional rendering. One example of such a tool is available under the name Raphael™ from Synopsys®, Inc. of Mountain View Calif. Raphael, however, can only convert a two dimensional IC layout rendering into a three dimensional layout rendering if the layout size is relatively small.
As such, what is needed is a method to convert a two dimensional IC layout rendering accurately and relatively quickly into alternate view renderings such as three dimensional and sectional view renderings.